ETRGEDG=NONE, LDRB=NONE, SBSMPLR=ONE, BURST=NONE, LDRA=NONE, TCCLKS=TIMER_CLOCK1
Channel Mode Register (channel = 0)
| TCCLKS | Clock Selection 0 (TIMER_CLOCK1): Clock selected: internal PCK6 clock signal (from PMC) 1 (TIMER_CLOCK2): Clock selected: internal MCK/8 clock signal (from PMC) 2 (TIMER_CLOCK3): Clock selected: internal MCK/32 clock signal (from PMC) 3 (TIMER_CLOCK4): Clock selected: internal MCK/128 clock signal (from PMC) 4 (TIMER_CLOCK5): Clock selected: internal SLCK clock signal (from PMC) 5 (XC0): Clock selected: XC0 6 (XC1): Clock selected: XC1 7 (XC2): Clock selected: XC2 |
| CLKI | Clock Invert |
| BURST | Burst Signal Selection 0 (NONE): The clock is not gated by an external signal. 1 (XC0): XC0 is ANDed with the selected clock. 2 (XC1): XC1 is ANDed with the selected clock. 3 (XC2): XC2 is ANDed with the selected clock. |
| LDBSTOP | Counter Clock Stopped with RB Loading |
| LDBDIS | Counter Clock Disable with RB Loading |
| ETRGEDG | External Trigger Edge Selection 0 (NONE): The clock is not gated by an external signal. 1 (RISING): Rising edge 2 (FALLING): Falling edge 3 (EDGE): Each edge |
| ABETRG | TIOAx or TIOBx External Trigger Selection |
| CPCTRG | RC Compare Trigger Enable |
| WAVE | Waveform Mode |
| LDRA | RA Loading Edge Selection 0 (NONE): None 1 (RISING): Rising edge of TIOAx 2 (FALLING): Falling edge of TIOAx 3 (EDGE): Each edge of TIOAx |
| LDRB | RB Loading Edge Selection 0 (NONE): None 1 (RISING): Rising edge of TIOAx 2 (FALLING): Falling edge of TIOAx 3 (EDGE): Each edge of TIOAx |
| SBSMPLR | Loading Edge Subsampling Ratio 0 (ONE): Load a Capture Register each selected edge 1 (HALF): Load a Capture Register every 2 selected edges 2 (FOURTH): Load a Capture Register every 4 selected edges 3 (EIGHTH): Load a Capture Register every 8 selected edges 4 (SIXTEENTH): Load a Capture Register every 16 selected edges |